SCOC=0, SDOD=000, EXCYC=0, SDODCS=0, SOCWP=0, SDOC=0
Output Control Register
| SDOC | SDA Output Control 0 (0): I3C drives the SDAn pin low. 1 (1): I3C releases the SDAn pin. |
| SCOC | SCL Output Control 0 (0): I3C drives the SCLn pin low. 1 (1): I3C releases the SCLn pin. |
| SOCWP | SCL/SDA Output Control Write Protect 0 (0): Bits SCOC and SDOC are protected. 1 (1): Bits SCOC and SDOC can be written (When writing simultaneously with the value of the target bit). This bit is read as 0. |
| EXCYC | Extra SCL Clock Cycle Output 0 (0): Does not output an extra SCL clock cycle (default). 1 (1): Outputs an extra SCL clock cycle. |
| SDOD | SDA Output Delay 0 (000): No output delay 1 (001): 1 I3Cφ cycle (When OUTCTL.SDODCS = 0 (I3Cφ)) 1 or 2 I3Cφ cycles (When OUTCTL.SDODCS = 1 (I3Cφ/2)) 2 (010): 2 I3Cφ cycles (When OUTCTL.SDODCS = 0 (I3Cφ)) 3 or 4 I3Cφ cycles (When OUTCTL.SDODCS = 1 (I3Cφ/2)) 3 (011): 3 I3Cφ cycles (When OUTCTL.SDODCS = 0 (I3Cφ)) 5 or 6 I3Cφ cycles (When OUTCTL.SDODCS = 1 (I3Cφ/2)) 4 (100): 4 I3Cφ cycles (When OUTCTL.SDODCS = 0 (I3Cφ)) 7 or 8 I3Cφ cycles (When OUTCTL.SDODCS = 1 (I3Cφ/2)) 5 (101): 5 I3Cφ cycles (When OUTCTL.SDODCS = 0 (I3Cφ)) 9 or 10 I3Cφ cycles (When OUTCTL.SDODCS = 1 (I3Cφ/2)) 6 (110): 6 I3Cφ cycles (When OUTCTL.SDODCS = 0 (I3Cφ)) 11 or 12 I3Cφ cycles (When OUTCTL.SDODCS = 1 (I3Cφ/2)) 7 (111): 7 I3Cφ cycles (When OUTCTL.SDODCS = 0 (I3Cφ)) 13 or 14 I3Cφ cycles (When OUTCTL.SDODCS = 1 (I3Cφ/2)) |
| SDODCS | SDA Output Delay Clock Source Selection 0 (0): The internal reference clock (I3Cφ) is selected as the clock source of the SDA output delay counter. 1 (1): The internal reference clock divided by 2 (I3Cφ/2) is selected as the clock source of the SDA output delay counter. |